Clock gating/power gating that stop supplying to a circuit(s), a clock signal/source voltage that is not necessary for operation are conventionally known as techniques to reduce power consumption of a semiconductor integrated circuit (hereinafter, “first conventional technology”). Voltage reduction and the provision of multiple power sources are also known as techniques to reduce power consumption (hereinafter, “second conventional technology”).
The use of a data holding element (hereinafter, “first flip flop (FF)”) that takes in data in synchronization with the rising edge of a clock signal and/or a data holding element (hereinafter, “second FF”) that takes in data in synchronization with the falling edge of a clock signal (hereinafter, “third conventional technology”) is known as a technique for reducing clock skew and noise (see, for example, Japanese Laid-Open Patent Publication Nos. 2000-29562, 2003-347404, and 2007-110403).
However, the first conventional technology cannot be applied to a circuit in which a clock path needs to be operated continuously. The second conventional technology cannot reduce the source voltage when a clock path is always operated fast, since the reduction of the source voltage causes slow operation of the semiconductor integrated circuit.
The third conventional technology propagates a clock signal input into the first FF and the second FF by clock buffers each of which includes multiple gates. Thus, a non-inverting clock buffer that includes an even number (2 or more) of gates is always inserted when non-inverting logic is required, thereby increasing the number of gates on the clock path.